hardware
Latency
The delay between an input and its visible result; FPGA recreations can keep this very low because logic runs in parallel hardware. Defined in the FPGA and the MiSTer Project entry of the archive.
hardware
The delay between an input and its visible result; FPGA recreations can keep this very low because logic runs in parallel hardware. Defined in the FPGA and the MiSTer Project entry of the archive.